Presented by Satyajit Das.
Coarse Grained Reconfigurable Arrays (CGRAs) are emerging as a low power computing alternative providing a high grade of acceleration. However, the area and energy efficiency of these devices are bottlenecked by the configuration/context memory when they are made autonomous and loosely coupled with CPUs. The size of these context memories is of prime importance due to their high area and impact on power consumption. For instance, a 64-word context memory typically represents 40% of a processing element area. In this context, since traditional mapping approaches do not take the size of the context memory into account, CGRAs often become oversized which strongly degrade their performance and interest. In this work, we proposed a context memory aware mapping for CGRAs to achieve better area and energy efficiency. In my talk, I will describe the proposed mapping approach which tries to find at least one mapping solution for a given set of constraints defined by the context memories of the PEs. Another important aspect of application mapping is addressed in this work, which is to support floating point applications onto CGRAs. With the recent advancements in algorithms and performance requirements of applications, supporting only integer and logical arithmetic limits the interest of classical/traditional CGRAs. In this work, we proposed a novel CGRA architecture and associated compilation flow supporting both integer and floating-point computations for energy efficient acceleration. In my talk, I will also speak about the proposed architecture and compilation flow supporting floating point operations onto CGRAs.