Valentin Besnard (PhD student)
The increasing complexity of embedded systems leads to uncertain behaviors, security flaws, and design mistakes. With model-based engineering, early diagnosis of such issues is made possible by verification tools working on design models. However, three severe drawbacks remain to be fixed. First, transforming design models into executable code creates a semantic gap between models and code. Furthermore, for formal verification, a second transformation (towards a formal language) is generally required, which complicates the diagnosis process. Finally, an equivalence relation between verified formal models and deployed code should be built, proven, and maintained. To tackle these issues, we introduce a UML interpreter that fulfills multiple purposes: simulation, formal verification, and execution on both desktop computer and bare-metal embedded target. Using a single interpreter for all these activities ensures operational semantics consistency. We illustrate our approach on a level crossing example, showing verification of LTL properties on a desktop computer, as well as execution on a stm32 embedded target.
Arnaud Tisserand (DR CNRS)
Asymmetric cryptography is a key element in secure systems. Key exchange, digital signature and specific cyphering protocols are mandatory in some secure applications (e.g. embedded systems, WSNs, IoT, internet applications). Elliptic Curve Crypto (ECC) is the current standard for asymmetric crypto in most of countries. We will present what are the basic notions in ECC, what types of computations are performed, examples of crypto protocols, some implementation aspects and protections against physical attacks. This seminar does not assume specific mathematical background.
Soultana Ellinidou (phd student), Gaurav Sharma (post-doc researcher)
University: Cyber security research center, Université libre de Bruxelles (ULB)
In recent years, Multi Processor System-on-Chips (MPSoCs) are widely deployed in embedded applications. The Cloud-Of-Chips (CoC) is a scalable MPSoC architecture comprised of a variable number of interconnected Integrated Circuits (IC) and Processing Clusters (PC). The Network on Chip (NoC) is now the de facto way of on-chip communication for any scalable MPSoC architecture. The Software Defined Networking (SDN) can be a viable alternative to reduce the current NoC complexity by decoupling the control logic from physical to software layer. Security on SDNoC is of high interest. For instance, in order to execute a sensitive application on an MPSoC platform, a number of PCs is allocated. These PCs create a virtual zone to run the application securely. The creation of such security zones can be easily managed with the help of SDN approach.
Title: Accelerating the Adoption of Unikernels
Abstract: Unikernels are specialized and lightweight virtualized guests that can be viewed as an application of the Exokernel/LibOS model to the cloud. While they provide multiple benefits in various application domains, unikernels struggle to gain widespread popularity due to several limitations. In this presentation, we will address some of these limitations, in particular the difficulty to port existing/legacy applications to current unikernel models.
Bio: Pierre Olivier achieved his PhD degree from University of South/Western Brittany in 2014. Afterwards he joined Virginia Tech for a postdoc, and he is now a research assistant professor there. His research interests include operating systems, virtualization, storage management, performance/energy analysis and improvement, as well as heterogeneous systems.
Title: Optimizing Memory/Storage Systems for Big Data Applications
Abstract: Optimizing memory/storage is one of the most critical issues in big data systems as huge amount of data need to be stored/transferred/processed in memory and storage devices. In this talk, I will introduce our recent work in optimizing memory/storage systems for big data applications. In particular, I will present an approach by deeply integrating device and application to optimize flash-based key-value caching – one of the most important building blocks in modern web infrastructures and high-performance data-intensive applications. I will also briefly talk about the challenges and opportunities by utilizing the NVDIMM (Non-Volatile Dual In-line Memory Module) technologies to reduce the long I/O latency for big data workloads. Finally, I will introduce the department of computing at Hong Kong Polytechnic University (i.e. staff, student, curriculum, management, etc.).
Bio: Zili Shao is an Associate Professor and Associate Head in the Department of Computing, Hong Kong Polytechnic University, Hong Kong. He received the B.E. degree in electronic mechanics from the University of Electronic Science and Technology of China, China, in 1995, and the M.S. and the Ph.D. degrees from the Department of Computer Science, University of Texas at Dallas, Dallas, TX, USA, in 2003 and 2005, respectively. His current research interests include embedded software and systems, storage systems and related industrial applications.
Les teasers sont disponibles dans la pièce jointe.
Le séminaire poster permet de réunir les collègues de toute l'équipe et d'échanger autour d'un poster, déjà présenté lors d'une manifestation scientifique ou créé pour l'occasion.
Chaque poster fait l'objet d'un "teaser", présenté devant l'assemblé.
Un template pour vous aider à élaborer une seule planche qui résume rapidement le poster est proposé.
Utiliser le template n'est pas obligatoire. Une seule règle : une seule page en pdf !
à renvoyer à Kevin Martin pour le 5/06/2018 à 18h.
Rendez vous à l'amphi B à 12h (UFR sciences, 6 av le Gorgeu à Brest).
Les posters sont à afficher entre 12h et 13h30 dans le hall au dessus de l'amphi B.
Rendez-vous pour tout le monde à 13h30 dans le hall au dessus de l'amphi B.
Présentation de tous les posters en mode "teaser" (90 secondes) à partir de 13h30.
Un café sera apporté vers 14h en haut de l'amphi B et nous pourrons alors faire le tour des posters.
Bilan et fin du séminaire prévus vers 16h/16h30.
Mourad Dridi, doctorant en troisième année sous la direction de Frank Singhoff
Titre1: DAS: An Efficient NoC Router for Mixed-Criticality Real-Time Systems
Titre2: Mixed-Criticality System and Network-on-Chip: A Dual Task and Flow Model
Mixed-Criticality Systems are real-time systems characterized by two or more distinct levels of criticality. In MCS, it is imperative that high-critical ﬂows meet their deadlines while low-critical ﬂows can tolerate some delays. Sharing resources between ﬂows in Network-On-Chip (NoC) can lead to different unpredictable latencies and subsequently complicate the implementation of MCS in many-core architectures. This talk will present ongoing work at Lab-STICC to enforce mixed-criticality requirements deployed over NoCs. We propose task and communication models to investigate their schedulability. Furthermore, a specific NoC router design is proposed and validated.
Over the past decade, a wide-ranging collection of network functions in middleboxes has been used to accommodate the needs of network users. Although the use of general-purpose processors has been shown to be feasible for this purpose, the serial nature of microprocessors limits network functional virtualization (NFV) performance. In this talk, we describe a new heterogeneous hardware-software approach to NFV construction that provides scalability and programmability, while supporting significant hardware-level parallelism and reconfiguration. Our computing platform uses both field-programmable gate arrays (FPGA) and microprocessors to implement numerous NFV operations that can be dynamically customized to specific network flow needs. Traffic management and hardware reconfiguration functions are performed by a global coordinator that allows for the rapid sharing of middlebox state and continuous evaluation of network function needs. To evaluate our approach, a series of software tools and NFV modules have been implemented. Our system is shown to be scalable for collections of network functions exceeding one million shared states.
Russell Tessier has worked in the research area of reconfigurable computing for the past 25 years. In addition to being a professor, he is the Associate Dean of Graduate Studies for the UMass College of Engineering. His current research interests include security for field-programmable gate arrays, networks-on-chip, and embedded systems.
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